The present invention relates to a circuit for correcting distortion of an image on a screen in an image displaying apparatus having a cathode-ray tube, such as a display monitor.
In an image displaying apparatus having a cathode-ray tube, such as a display monitor, an image produced on a screen through deflection of an electron beam has distortion (referred to as xe2x80x9cdeflection-distortionxe2x80x9d hereinafter) depending on the form of the cathode-ray tube etc. Therefore, a deflection-distortion correcting circuit that generates a deflection-distortion correcting signal is used to adjust the extent of deflection and correct the deflection-distortion of an image on a screen. The above-described deflection-distortion correcting signal is generated by an analog circuit, however, it is not necessarily possible to obtain a deflection-distortion correcting signal having the desired accuracy. Accordingly, with the aim of improving the accuracy of such a deflection-distortion correcting signal, a deflection-distortion correcting circuit has been proposed that generates a deflection-distortion correcting signal based on digital data.
FIG. 10 is a block diagram of such a deflection-distortion correcting circuit. The deflection-distortion correcting circuit shown in FIG. 10, described in Japanese Unexamined Patent Publication No. 5-328163, generates a deflection-distortion correcting signal on the basis of digital data. In FIG. 10, there is shown a horizontal-deflection circuit 5, a horizontal-deflection power supplying circuit 6 of the series type, a horizontal-deflection current output circuit 7, a horizontal-deflection coil 8, a deflection-distortion .correcting circuit 21, a period-discriminating circuit 22, a period/N-generating circuit 23, an output-level control circuit 24, a counter circuit 25, a D/A conversion circuit 26, and an inverting/amplifying circuit 27.
The operation of the above deflection-distortion correcting circuit 21 shown in FIG. 10 will be explained below. The counter circuit 25 is reset by level change of a vertical synchronizing signal, and starts a count of clock pulses produced by frequency-dividing a reference clock in the period/N-generating circuit 23. The count data (digital data) of the counter circuit 25 is converted into an analog signal by the D/A conversion circuit 26, inverted in signal polarity by the inverting/amplifying circuit 27 as necessary, and is adjusted in signal amplitude (Here, it is assumed that the signal polarity is not inverted, and the analog signal output from the inverting/amplifying circuit 27 increases linearly). The analog signal which is generated from this digital data and increases linearly is output from the deflection-distortion correcting circuit 21 to the horizontal-deflection power supplying circuit 6 as a deflection-distortion correcting signal.
The horizontal-deflection power supplying circuit 6 has an internal structure as shown in FIG. 2. The source voltage Vout which the horizontal-deflection power supplying circuit 6 supplies to the horizontal-deflection current output circuit 7 is modulated by the deflection-distortion correcting signal Sb input from the deflection-distortion correcting circuit 21. The horizontal-deflection current output circuit 7 generates a horizontal-deflection current using the voltage Vout modulated by the deflection-distortion correcting signal Sb as its electric power, and supplies it to the coil 8. The coil 8 generates a horizontal-deflection magnetic field according to the supplied horizontal-deflection current. The envelope characteristic of the peak values of the above-described horizontal-deflection current varies according to the modulated source voltage Vout. Thus, deflection-distortion in that a monitor screen is distorted to a trapezoidal shape can be corrected.
FIG. 11(a) shows a waveform of the deflection-distortion correcting signal Sb generated by the deflection-distortion correcting circuit 21 of FIG. 10, and the source voltage Vout modulated by this deflection-distortion correcting signal Sb. FIG. 11(b) shows a waveform of the deflection-distortion correcting signal Sb generated by the deflection-distortion correcting circuit 21, and the source voltage Vout modulated by this deflection-distortion correcting signal Sb, in a case where a vertical blanking signal is used instead of the vertical synchronizing signal in FIG. 10. The vertical blanking signal is a signal whose level during an image display period (including horizontal blanking periods) over which a video signal exists is different from that during a vertical blanking period over which no image signal exists, to enable detecting a vertical blanking period. FIG. 11(c) shows a monitor screen corrected by the source voltage Vout modulated by the deflection-distortion correcting signal Sb of FIG. 11(a) or 11(b). In FIG. 11(a) and FIG. 11(b), the dotted line represents a waveform of the deflection-distortion correcting signal Sb which increases linearly, and the source voltage Vout modulated normally by this deflection-distortion correcting signal, and the solid line represents a waveform of the source voltage Vout distorted by parasitic inductance in the horizontal-deflection power supplying circuit 6. In FIG. 11(c), the chain line represents a monitor screen distorted to a trapezoidal shape before correction, the dotted line represents a monitor screen corrected by the source voltage modulated normally, and the solid line represents a monitor screen corrected by the distorted source voltage.
If the source voltage Vout is normally modulated as shown by the dotted line in FIG. 11(a) in the horizontal-deflection power supplying circuit 6 according to the deflection-distortion correcting signal Sb which increases linearly, the monitor screen distorted to the trapezoidal shape as shown by the chain line in FIG. 11(c) is corrected normally as shown by the dotted line in FIG. 11(c).
However, the above-described conventional deflection-distortion correcting circuit involves a problem, which will be explained below.
FIG. 12 is an equivalent circuit diagram of the power supplying circuit 6 of the series type in a case where parasitic inductance is not negligible. In FIG. 12, the reference numerals identical to those in FIG. 2 represent the same elements. The horizontal-deflection power supplying circuit 6 of FIG. 12 differs from the horizontal-deflection power supplying circuit 6 of FIG. 2 in that an inductive load 30 appears between an emitter electrode of a transistor 16 and an output terminal of the source voltage Vout due to the parasitic inductance. Although inductance components (parasitic inductance) of capacitors 18 and 19 and a wiring pattern are negligible for a low frequency signal, they are not negligible for a high frequency signal, and therefore, the inductive load 30 appears as shown in FIG. 12.
In the deflection-distortion correcting circuit 21 of FIG. 10, the moment the counter circuit 25 is reset by the vertical synchronizing signal, the digital data changes instantaneously from the maximum value to the minimum value, and therefore the deflection-distortion correcting signal as well changes instantaneously from the maximum value to the minimum value. Accordingly, the deflection-distortion correcting signal includes a high frequency component. When the deflection-distortion correcting signal having such a high frequency component is input into the horizontal-deflection power supplying circuit 6, the above-described inductance component in the horizontal-deflection power supplying circuit 6 cannot be neglected, and the inductive load 30 appears as a factor in the horizontal-deflection power supplying circuit 6 as shown in FIG. 12.
When the inductive load 30 appears, the source voltage Vout for horizontal deflection is not normally modulated according to the deflection-distortion correcting signal Sb, and consequently, it has a distorted waveform as shown by the solid line in FIG. 11(a) which includes phase delay, reflection, ringing, etc. The monitor screen corrected by such a distorted source voltage Vout will have abnormal curves and distortion ranging from the upper part to the middle part thereof as shown by the solid line in FIG. 11(c).
In the deflection-distortion correcting circuit 21 of FIG. 10, in a case where the counter circuit 25 is arranged to be reset, not by the vertical synchronizing signal, but by a vertical blanking signal having a pulse width larger than the vertical synchronizing signal as soon as an image display period terminates, the deflection-distortion correcting signal Sb stays at the minimum value, during a blanking period, and increases linearly during an image display period. The level of the above-described vertical blanking signal during an image display period (including horizontal blanking periods) over which a video signal exists is different from that during a vertical blanking period over which no image signal exists, to enable detecting a vertical blanking period. If the source voltage Vout for horizontal deflection is normally modulated as shown by the dotted line in FIG. 11(b) by the deflection-distortion correcting signal Sb, the monitor screen distorted to a trapezoidal shape as shown by the chain line in FIG. 11(c) due to deflection-distortion is normally corrected as shown by the dotted line in FIG. 11(c). However, even if the counter circuit 25 is reset by a vertical blanking signal, the source voltage Vout for horizontal deflection may have a distorted waveform as represented by the solid line in FIG. 11(b) which includes phase delay, reflection, ringing, etc. A monitor screen corrected by such a distorted source voltage Vout will have abnormal curves and distortion ranging from the upper part to the middle part thereof as shown by the solid line in FIG. 11(c).
As described above, in the conventional deflection-distortion correcting circuit, since the value of the deflection-distortion correcting signal Sb changes from the maximum to the minimum abruptly, and consequently, the deflection-distortion correcting signal Sb has a high frequency component, the source voltage Vout for horizontal deflection modulated by this deflection-distortion correcting signal Sb in the, horizontal-deflection power supplying circuit is easily affected by the parasitic inductance in the horizontal-deflection power supplying circuit 6, causing the problem that phase delay, reflection, ringing, etc. arise in the source voltage Vout, which brings abnormal curves and distortion to the screen.
The present invention has been made in order to solve the above-described problem with an object of providing a deflection-distortion correcting circuit that does not bring abnormal curves and distortion to a screen.
This object is achieved by a deflection-distortion correcting circuit for correcting deflection-distortion of an image by modulating a source voltage for horizontal deflection, said deflection-distortion correcting circuit comprising:
a first correcting data generator generating a first correcting data for an image display period;
a second correcting data generator generating a second correcting data for a vertical blanking period;
a deflection-distortion correcting signal generator generating a correcting signal for said image display period and said vertical blanking period in accordance with said first and second correcting data; and
a modulator modulating said source voltage with said correcting signal,
wherein, said second correcting data generator generates said second correcting data such that said correcting signal has a value, at a start of a vertical blanking period, which is equal to a value of said correcting signal at an end of an image display period, and that said correcting signal decreases or increases monotonously during the whole period of the vertical blanking period and reaches, at an end of the vertical blanking period, a value at a start of the image display period.
The second correcting data generator may generate said second correcting data such that said correcting signal varies linearly over the vertical blanking period.
The second correcting data generator may also generate said second correcting data such that said correcting signal varies along a monotonously decreasing or increasing curve of a second order or higher over the vertical blanking period.
The first correcting data generator may generate said first correcting data such that said correction signal is also a signal for correcting side-pin distortion of an image during the image display period.
The second correcting data generator can be a microcomputer, and said second correcting data for the vertical blanking period can be produced by an operation in said microcomputer.